1. Field of the Invention:
This invention relates to a semiconductor device, and more particularly to a semiconductor device including a MOS element, such as a semiconductor device (hereinafter called "Bi-MOS element") in which both a bipolar element and a MOS element are formed on a MOS field effect transistor (hereinafter called "MOSFET") or a single semiconductor substrate and a method of manufacturing such semiconductor device.
2. Description of the Related Art:
As advances have recently been made in integrating elements in a large scale in MOS semiconductor IC devices, application of a buried contact structure is on the rise.
In a typical buried contact structure in conventional MOSFETs, a gate electrode and a source electrode and/or a drain electrode (hereinafter called "source/drain electrode") are formed during the growth and process of one and the same polycrystalline silicon, and a contact with a source diffused region or a drain diffused region (hereinafter called "source/drain diffused region") is formed via a contact diffused region by impurity diffusion from the source/drain electrode.
In response to the minute elements, an LDD (Lightly Doped Drain) structure as a measure against the hot electron problem was used in MOSFET.
The structure of this type semiconductor device is schematically shown in FIG. 2 of the accompanying drawings.
In FIG. 2, MOSFET is an n-channel MOS transistor having an LDD structure. This MOSFET 100 has a buried contact structure on a p-type silicon substrate 10. A contact diffused region 28 constituting this buried contact structure is formed of an n.sup.+ diffusion layer formed by impurity diffusion from a source/drain electrode 40 formed of an n.sup.+ -type polycrystalline silicon layer. The source/drain electrode 40 is formed together with a wiring portion 44 while the layer of a gate electrode 30 is formed. The n.sup.+ -type contact diffused region 28 is connected to one n.sup.+ -type source/drain diffused region 42a via an n.sup.- -type offset region 52 which is located right under a side wall 50 contiguous to the source/drain electrode 40.
In FIG. 2, reference numeral 12 designates a field oxide film; 14, a gate oxide film; and 18, a silicon layer hollow formed during etching the polycrystalline silicon layer.
However, the semiconductor device of FIG. 2 has the following problems resulting from the buried contact structure:
(1) If an impurity having a small diffusion constant is used as the impurity in the source/drain electrode 40 of the n.sup.+ -type polycrystalline silicon, the connection of the n.sup.+ -type contact diffused region 28 would be shallow. The connection of the n.sup.- -type offset region 52 to be connected to the n.sup.+ -type contact diffused region 28 is originally shallow and has a high resistance. Therefore, the resistance of the whole buried contact structure would increase to add a high parasitic resistance to the source/drain diffused region 42a of MOSFET, thus impairing the mutual conductance of MOSFET and the characteristic of the on current adapted to flow when the transistor is in on state.
(2) During formation of the n.sup.+ -type gate electrode 30 and the n.sup.+ -type source/drain electrode 40 by etching, the exposed portion of the p-type silicon substrate 10 also would be etched to form the silicon layer hollow 18. If the n.sup.- -type offset region 52 is formed by ion implantation, the impurity would hardly be doped to the peripheral portion of the silicon layer hollow 18 so that the impurity concentration of the n.sup.- -type offset region 52 to be formed tends to become lower than a predetermined value while the resistance of the same n.sup.- -type offset region 52 tends to become increased. As a result, the function of the LDD structure would work inadequately and thereby cause the above problem (1). This also results in irregularity of the above-mentioned characteristic due to non-uniform processing, such as in the etching step.
The foregoing problems are remarkable if arsenic having a small diffusion constant is used as the impurity in the n.sup.+ -type polycrystalline silicon layer (source/drain electrode 40), the n.sup.- -type offset region 52 and the n.sup.+ -type source/drain diffused regions 42a, 42b.
Further, for the same reason, the above problem (1) will be caused even in the case of MOSFET having a buried contact structure to which an LDD structure is not added.
Also in the case of a Bi-MOS element, when forming an n.sup.+ -type emitter diffused region of the bipolar transistor, the same problem as with the MOSFET would occur due to the impurity diffusion of arsenic from the n.sup.+ -type polycrystalline silicon layer.
In order to realize a high-speed bipolar transistor, the connection of the n.sup.+ -type emitter diffused region should be shallow. Therefore, when forming a contact diffused region of MOSFET simultaneously with the emitter diffused region, the connection of the contact diffused region would be shallow and thereby cause the above problems (1) and (2). Consequently, if in a Bi-MOS element a parasitic resistance resulting from the buried contact structure is to be reduced, the connection of the diffused region should be deep. This would be an obstacle to a high-speed Bi-MOS element.